The present invention relates to a semiconductor device and manufacturing technology thereof and, more particularly, to technology effective when applied to a semiconductor device in which a wiring board and a semiconductor chip mounted over the main surface thereof are electrically coupled with a wire.
Patent Document 1 (Japanese Patent Laid-Open No. 2005-191447) discloses a semiconductor device in which a wiring board and a semiconductor chip (hereinafter, referred to only as a chip) mounted over the main surface of the wiring board are electrically coupled with a wire (bonding wire).
On the main surface of the chip mounted over the wiring board, a plurality of pads including pads in a power source system (bonding pads) and pads in a signal input/output system is arranged in two columns and in a staggered manner. The width of the power source system pad is greater than that of the signal input/output system pad and the diameter of a wire coupled to the power source system pad is larger than that of a wire coupled to the signal input/output system pad. Further, by making the loop height of the wire coupled to the pad of the pads arranged in the two columns, which is in the inner column of the chip, different from that of the wire coupled to the pad of the pads arranged in the two columns, which is in the outer column, and bonding the wire with the higher loop height after bonding the wire with the lower loop height, neighboring wires are prevented from coming into contact.
Patent Document 2 (Japanese Patent Laid-Open No. 2003-338519) discloses a semiconductor device in which pads on the main surface of a chip are arranged in two columns and in a staggered manner as in Patent Document 1. In the semiconductor device, in the first and second wires of a plurality of wires electrically coupling the pad of the chip and the coupling part of a wiring board, which are adjacent to each other, the loop height of the second wire is made greater than that of the first wire and one end part of the second wire is coupled to the pad at a position farther away from one side of the chip than one end part of the first wire. Further, the other end part of the second wire is coupled to the coupling part of the wiring board at a position farther away from one side of the chip than the other end part of the first wire.
Patent Document 3 (Japanese Patent Laid-Open No. 1993-243307) discloses technology to prevent the deformation of a wire (wire flowing) when sealing a chip and the wire with a resin by constituting a wire (wire longer than other wires) of a plurality of wires electrically coupling the pad of the chip and the lead of a lead frame, which is located in the vicinity of a corner part of the chip, by a rigid wire or a thick wire.
Patent Document 4 (Japanese Patent Laid-Open No. 1996-236564) discloses technology to prevent the wire flowing by changing the diameters of a plurality of wires coupling the pad of a chip and the lead of a lead frame according to the position of the pad arranged on the main surface of the chip. Specifically, the technology to make larger the diameter of the wire to be coupled to the pad in the vicinity of the corner part of the chip than the diameter of the other wires, or the technology to make larger the diameter of the wire coupled in the direction along an interface in which a resin injected into a molding die flows than the diameter of the wire coupled in the direction crossing the interface, etc., is employed.